The present embodiments relate to electronic circuit manufacture and are more particularly directed to improving recessed drain extensions in a transistor device.
Semiconductor devices are prevalent in all aspects of electronic circuits, and an often critical and dominant element used in such circuits is the transistor. Thus, due to the evolution of electronic design and its criteria, considerable effort has been made to improve transistor design. One approach currently being implemented involves creating so-called silicon strain in the transistor channel through the use of recessed silicon-germanium (SiGe) drain extensions. Generally, various steps occur in this context. First, a transistor gate stack is formed in a fixed relationship relative to a semiconductor substrate. Next, a portion or all of the gate sidewall is built. When only a portion of the sidewall is built, that portion is sometimes referred to as a spacer and typically includes one or more layers formed on the vertical side surfaces of the transistor gate. Next, an etch is performed into the silicon substrate, thereby forming a “recess” laterally extending outward from both sides of the transistor gate and its sidewall or sidewall spacer. The recess is thereafter filled with an epitaxial deposition of SiGe, with the resulting SiGe regions being the “drain extensions.” Due to the differing nature of the SiGe as compared to the silicon substrate beneath it, a mis-match is created in the lattice between these two different semiconductor materials, where the SiGe lattice is larger than that of the underlying silicon. The resulting lattice mis-match creates forms a “strain” in the transistor channel, which is located beneath the transistor gate stack. This strain has been found to enhance mobility in the transistor channel, thereby improving device performance.
While the preceding approach to recessed SiGe drain extensions has improved upon other transistor technologies, the present inventor has observed certain drawbacks with respect to this approach. Specifically, in order to perform the epitaxial deposition of SiGe in the device recesses as discussed above, a high-quality surface at the location of the recess is desirable. However, it has been observed that the imperfections of, and at, the silicon surface of the recess may compromise the quality of the epitaxial SiGe deposition. Indeed, the prior art has implemented certain approaches in attempting to reduce this effect, where a particular approach depends on the extent to which the sidewall spacer is completed at the time the approach is taken. Specifically, in one approach, when only two layers of the sidewall spacer are in place, sometimes referred to in current technology as an “offset spacer” (meaning the entirety of all layers forming the spacing sidewall are not yet complete), the recess is formed and then an hydrofluoric (HF) acid wash is used at that point to remove impurities in the recess, followed by the epitaxial SiGe deposition. Note that the HF wash does not affect the sidewall spacer layers to a large extent at that point because typically the second sidewall spacer layer is nitride, which is resistant to the HF and, thus, protects the underlying layer between it and the transistor gate. Alternatively, in another approach, when the entire spacing sidewall is complete by adding more layers to it, the recess is formed and a remote plasma with a fluorine-based chemistry is used. While this latter approach is workable when the spacing sidewall is complete, it is noted in connection with the preferred embodiments, detailed below, that it is not preferable when cleaning the drain recesses at offset spacer layers due to the then-exposed nitride spacer layer, which cannot properly resist the fluorine plasma chemistry.
Thus, in view of the above, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.